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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications FEATURES: * Multi-Purpose 8-bit 8051 Family Compatible Microcontroller Unit (MCU) with Embedded SuperFlash Memory Fully Software and Development Toolset Compatible as well as Pin-For-Pin Package Compatible with Standard 8xC5x Microcontrollers 256 Bytes Register/Data RAM 20/36 KByte Embedded High Performance Flexible SuperFlash EEPROM - One 16/32 KByte block (128-Byte sector size) - One 4 KByte block (64-Byte sector size) - Individual Block Security Lock with SoftlockTM feature - 87C5x Programmer Compatible - Concurrent Operation during In-Application ProgrammingTM(IAPTM) - Memory Re-Mapping for Interrupt Support during IAP Support External Address Range up to 64 KByte of Program and Data Memory * High Current Drive on Port 1 (5, 6, 7) pins * Three 16-bit Timer/Counter * Programmable Serial Port (UART) * Six Interrupt Sources at 2 Priority Levels * Selectable Watchdog Timer (WDT) * Four 8-bit I/O Ports (32 I/O Pins) * TTL- and CMOS-Compatible Logic Levels * Extended Power-Saving Modes - Idle Mode - Power Down Mode with External Interrupt Wake-up - Standby (Stop Clock) Mode * High Speed Operation at 5 Volts (0 to 33MHz) * Low Voltage (2.7V) Operation (0 to 12MHz) * PDIP-40, PLCC-44 and TQFP-44 Packages * Temperature Ranges: - Commercial (0C to +70C) - Industrial (-40C to +85C) via a standard 87C5x OTP EPROM programmer fitted with a special adapter and firmware for SST89C54/58 devices. During the power-on reset, the SST89C54/58 can be configured as a master for source code storage or as a slave to an external host for In-Application Programming (IAP) operation. SST89C54/58 is designed to be programmed "In-System" and "In-Application" on the printed circuit board for maximum flexibility. The device is pre-programmed with a sample bootstrap loader in the memory (see Note 1), demonstrating the initial user program code loading or subsequent user code updating via the "IAP" operation. In addition to 20/36 KByte of SuperFlash EEPROM program memory on-chip, the SST89C54/58 can address up to 64 KByte of program memory external to the chip. The SST89C54/58 have 256 x 8 bits of on-chip RAM. Up to 64 KByte of external data memory (RAM) can be addressed. The highly reliable, patented SuperFlash technology and memory cell architecture have a number of important advantages for designing and manufacturing flash EEPROMs, when compared with other approaches. These advantages translate into significant cost and reliability benefits for our customers.
Note 1: The sample bootstrap loader is for the user's reference and convenience only. SST does not guarantee the functionality or the usefulness of the sample bootstrap loader. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
*
* *
*
PRODUCT DESCRIPTION SST89C54 and SST89C58 are members of the FlashFlex51 family of 8-bit microcontrollers. The FlashFlex51 family is a family of embedded microcontroller products designed and manufactured on the state-of-the-art SuperFlash CMOS semiconductor process technology. As a member of the FlashFlex51 controller family, the SST89C54/58 uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with standard 8xC5x microcontroller devices. SST89C54/58 comes with 20/36 KByte of integrated on-chip flash EEPROM program memory using the patented and proprietary Silicon Storage Technology, Inc. (SST) CMOS SuperFlash EEPROM technology with the SST field enhancing tunneling injector split-gate memory cells. The SuperFlash memory is partitioned into 2 independent program memory blocks. The primary SuperFlash Block 0 occupies 16/32 KByte of internal program memory space and the secondary SuperFlash Block 1 occupies 4 KByte of SST89C54/58's internal program memory space. The 4 KByte secondary SuperFlash block can be mapped to the highest or lowest location of the 64 KByte address space; it can also be hidden from the program counter and used as an independent EEPROM-like data memory. The flash memory blocks can be programmed
(c) 2000 Silicon Storage Technology, Inc. 344-2 8/00
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. FlashFlex, In-Application Programming, IAP and SoftLock are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 1
FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications TABLE OF CONTENTS PRODUCT FEATURES ......................................................................................................................................... 1 PRODUCT DESCRIPTION .................................................................................................................................... 1 FUNCTIONAL BLOCKS ......................................................................................................................................... 4 Functional Block Diagram ............................................................................................................................... 4 PIN ASSIGNMENTS .............................................................................................................................................. 5 Pin Descriptions .............................................................................................................................................. 6 MEMORY ORGANIZATION ................................................................................................................................... 8 Program Memory ............................................................................................................................................ 8 Memory Re-Mapping ..................................................................................................................................... 10 Activation and Deactivation of Memory Re-Mapping ............................................................................... 11 Data Memory ................................................................................................................................................ 13 Special Function Registers (SFR) ................................................................................................................. 13 CPU Related SFRs .................................................................................................................................. 13 Flash Memory Programming SFRs .......................................................................................................... 14 Watchdog Timer SFRs ............................................................................................................................ 17 Timer/Counters SFRs .............................................................................................................................. 18 Interface SFRs ......................................................................................................................................... 18 FLASH MEMORY PROGRAMMING .................................................................................................................... 18 External Host Programming Mode ................................................................................................................ 18 Product Identification ............................................................................................................................... 20 External Host Mode Commands .............................................................................................................. 20 External Host Mode Clock Source ........................................................................................................... 21 Arming Command .................................................................................................................................... 21 Programming a SST89C54/58 ................................................................................................................. 21 Flash Operation Status Detection (Ext. Host Handshake) ....................................................................... 22 In-Application Programming Mode ................................................................................................................ 26 In-Application Programming Mode Clock Source ..................................................................................... 26 IAP Enable Bit ......................................................................................................................................... 26 In-Application Programming Mode Commands ........................................................................................ 26 Polling ...................................................................................................................................................... 29 Interrupt Temination ................................................................................................................................. 30 TIMERS/COUNTERS ........................................................................................................................................... 31
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications
SERIAL I/O (UART) .............................................................................................................................................. 31 WATCHDOG TIMER ............................................................................................................................................ 32 SECURITY LOCK ................................................................................................................................................ 32 Hard Lock ................................................................................................................................................. 32 SoftLock ................................................................................................................................................... 32 Status of the Security Lock ........................................................................................................................... 33 RESET ................................................................................................................................................................ 34 Power-On Reset ........................................................................................................................................... 34 POWER-SAVING MODES ................................................................................................................................... 35 CLOCK INPUT OPTIONS .................................................................................................................................... 37 ELECTRICAL SPECIFICATION ........................................................................................................................... 38 Absolute Maximum Ratings .......................................................................................................................... 38 Operation Range ........................................................................................................................................... 38 Reliability Characteristics .............................................................................................................................. 38 DC Electrical Characteristics ......................................................................................................................... 39 AC Electrical Characteristics ......................................................................................................................... 42 Explanation Of Symbols .......................................................................................................................... 43 External Clock Drive ................................................................................................................................ 44 Serial Port Timing - Shift Register Mode .................................................................................................. 45 PRODUCT ORDERING INFORMATION ............................................................................................................. 46 Part Number Valid Combinations .................................................................................................................. 46 PART NUMBER CROSS REFERENCE GUIDE .................................................................................................. 47 PACKAGING DIAGRAMS .................................................................................................................................... 48
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications FUNCTIONAL BLOCKS FUNCTIONAL BLOCK DIAGRAM
Program/Erase & IAP Control
RST VSS VDD ALE/PROG# PSEN# EA#
SuperFlash EEPROM 4K x 8
SuperFlash EEPROM 16/32K x 8
Port 0
8 I/O
Power Mode Management
T0 SFRs CPU T1 T2 Port 2 WDT Port 1
8 I/O
8 I/O
Bus Controller
Security Lock
Oscillator Mode Interrupt & Control Control Timing
8 RAM 256 x 8 8-bit UART Port 3 I/O
XTAL1 XTAL2
344 ILL B1.1
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications PIN ASSIGNMENTS
P1.1 (T2 Ex) P0.0 (AD0) P0.1 (AD1) P0.2 (AD2)
(T2) P1.0 (T2 Ex) P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5 (WR#) P3.6 (RD#) P3.7 XTAL2 XTAL1 VSS
1 2 3 4 5 6 7
40 39 38 37 36 35
VDD
P1.4 P1.3
P0.3 (AD3)
P1.0 (T2)
P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)
344 ILL F18.1
VDD
NC
P0.0 (AD0)
P1.2
1 2
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# NC ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13)
P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5
1 2 3 4 5 6 7 8 9 10 11
44 43 42 41 40 39 38 37 36 35 34 33
32 31 30
34 40-Pin PDIP 8 Top View 33 32 9 10 11 12 13 14 15 16 17 18 19 20 31 30 29 28 27 26 25 24 23 22 21
3 4 5 6 7
44-Pin TQFP Top View
29 28 27 26 25 24
23 12 13 14 15 16 17 18 19 20 21 22
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(WR#) P3.6
(RD#) P3.7
(A12) P2.4
XTAL2
XTAL1
VSS
344 ILL F19.1
FIGURE 1: PIN ASSIGNMENTS FOR 40-PIN PLASTIC DIP PI-PACKAGE
P1.1 (T2 Ex) P1.0 (T2)
FIGURE 2: PIN ASSIGNMENTS FOR 44-PIN TQFP TQJ-PACKAGE
P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3)
8 9 10
P1.4
P1.3
P1.2
6 P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5 7 8 9 10 11 12 13 14 15 16
5
4
3
2 1 44 43 42 41 40 39 38 37 36 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# NC ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13)
VDD
NC
11 12 13 14 15 16
44-Pin PLCC Top View
35 34 33 32 31 30
17 29 18 19 20 21 22 23 24 25 26 27 28
(WR#) P3.6 (RD#) P3.7 XTAL2 XTAL1 NC (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 VSS
FIGURE 3: PIN ASSIGNMENTS FOR 44-PIN PLCC NJ-PACKAGE
Note: NC pins must be left unconnected.
(c) 2000 Silicon Storage Technology, Inc.
344 ILL F20.1
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications TABLE 1: PIN DESCRIPTIONS Symbol Type1 P0[7:0] I/O1 Name and Functions Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external memory. In this application it uses strong internal pull-ups when transitioning to 1's. Port 0 also receives the code bytes during FLASH MEMORY programming, and outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can drive LS TTL inputs. Port 1 pins that have 1's written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current (IIL, on the data sheet) because of the internal pull-ups. P1(5, 6, 7) have high current drive of 16mA. Port 1 also receives the low-order address bytes during FLASH MEMORY programming and program verification. T2: (external count input to Timer/Counter 2), clock-out T2EX: (Timer/Counter 2 capture/reload trigger and direction control) Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1's written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current (IIL, on the data sheet) because of the internal pull-ups. Port 2 sends the high-order address byte during fetches from external Program memory and during accesses to external Data Memory that use 16-bit address (MOVX@DPTR). In this application it uses strong internal pull-ups when outputting 1's. During accesses to external Data Memory that use 8-bit addresses (MOVX@Ri), Port 2 sends the contents of the P2 Special Function Register. Port 2 also receives some control signals and a partial of high-order address bits during FLASH MEMORY programming and program verification. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers could drive LS TTL inputs. Port 3 pins that have 1's written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current (IIL, on the data sheet) because of the pull-ups. Port 3 also serves the functions of various special features of the FlashFlex51 Family. Port 3 also receives some control signals and a partial of high-order address bits during FLASH MEMORY programming and program verification. RXD: Serial input line TXD: Serial output line INT0#: External Interrupt 0 INT1#: External Interrupt 1 T0: Timer 0 external input T1: Timer 1 external input WR#: External Data Memory Write strobe RD#: External Data Memory Read strobe
P1[7:0]
I/O with internal pull-ups
P1[0] P1[1] P2[7:0]
I I I/O with internal pull-ups
P3[7:0]
I/O with internal pull-ups
P3[0] P3[1] P3[2] P3[3] P3[4] P3[5] P3[6] P3[7]
I O I I I I O O
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications PIN DESCRIPTIONS (CONTINUED) Symbol Type1 PSEN# O/I Name and Functions Program Store Enable: PSEN# is the Read strobe to External Program Memory. When the SST89C54/58 are executing from Internal Program Memory, PSEN# is inactive (high). When the device is executing code from External Program Memory, PSEN# is activated twice each machine cycle, except that two PSEN# activations are skipped during each access to External Data Memory. While the RST input is continually held high (for more than ten machine cycles), a forced high-to-low input transition on the PSEN# pin will bring the device into the "External Host" mode for the internal flash memory programming operation. Reset: A high logic state on this pin for two machine cycles (at least 24 oscillator periods), while the oscillator is running resets the device. After a successful reset is completed, if the PSEN# pin is driven by an input force with a high-to-low transition while the RST input pin is continually held high, the device will enter the "External Host" mode for the internal flash memory programming operation, otherwise the device will enter the "Normal" operation mode. External Access Enable: EA# must be connected to VSS in order to enable the SST89C54/58 to fetch code from External Program Memory locations starting at 0000h up to FFFFh. Note, however, that if the Security Lock is activated on either block, the logic level at EA# is internally latched during reset. EA# must be connected to VDD for internal program execution. The EA# pin can tolerate a high voltage2 of 12V (see Electrical Specification). Address Latch Enable: ALE is the output signal for latching the low byte of the address during accesses to external memory. This pin is also the programming pulse input (PROG#). Oscillator: Input and output to the inverting oscillator amplifier. XTAL1 is input to internal clock generation circuits from an external clock source. Power Supply: Supply voltage during normal, Idle, Power Down, and Standby Mode operations. Ground: Circuit ground. (0V reference)
I = Input O = Output It is not necessary to receive a 12V programming supply voltage during flash programming.
344 PGM T1.6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
RST
I
EA#
I
ALE/PROG#
I/O
XTAL1 XTAL2 VDD Vss
Note: 1 ) 2)
I O I I
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications MEMORY ORGANIZATION The SST89C54/58 have separate address spaces for program and data memory. Program Memory There are two internal flash memory blocks in the SST89C54/58. The primary flash memory Block 0 has 16/32 KByte and occupies the address space 0000h to 3FFFh/7FFFh. The secondary flash memory Block 1 has 4 KByte and occupies the address space F000h to FFFFh. The 16/32K x8 primary SuperFlash block is organized as 128/256 uniform sectors with sector address from A15 to A7. Each sector contains 2 rows with row address from A15 to A6. Each row has 64 Bytes with byte address from A5 to A0. The 4K x8 secondary SuperFlash block is organized as 64 uniform sectors with sector address from A15 to A6. Each sector contains 2 rows with row address from A15 to A5. Each row contains 32 Bytes with byte address from A4 to A0. Figure 4 shows the sector organization for SST89C54/58. When internal code operation is enabled (EA# = 1), the primary 16/32 KByte flash memory block is always visible to the program counter for code fetching. Figures 5 and 6 show the program memory organizations for the SST89C54/58. When internal code operation is enabled (EA# = 1), the secondary 4 KByte flash memory block is selectively visible for code fetching. The secondary block is always accessible through the SuperFlash mailbox registers: SFCM, SFCF, SFAL, SFAH, SFDT and SFST. When bit 7 of the SuperFlash Configuration mailbox register (SFCF[7]), SFR address location B1h, is set, the secondary 4 KByte block will be visible by program counter.
7FFFh Sector 255 7F80h
FFFFh Sector 63 FFC0h
89C58
4000h 3FFFh Sector 127 3F80h 89C54 007Fh Sector 0 0000h Block 0 (16/32 KByte) Primary F000h F03Fh Sector 0 Block 1 (4 KByte) Secondary
344 ILL F47.6
FIGURE 4: SECTOR ORGANIZATION
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications
EA# = 1 & SFCF[7] = 1 FFFFh F000h EFFFh 4 KByte INTERNAL
(Block 1)
EA# = 1 & SFCF[7] = 0 FFFFh FFFFh
EA# = 0
1 2
48 KByte EXTERNAL 44 KByte EXTERNAL
3
64 KByte EXTERNAL
4 5
4000h 3FFFh 16 KByte INTERNAL
(Block 0)
4000h 3FFFh 16 KByte INTERNAL
(Block 0)
6
0000h
344 ILL F21.1
0000h
0000h
7 8 9 10 11 12 13 14 15 16
FIGURE 5: SST89C54 PROGRAM MEMORY ORGANIZATION
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications
EA# = 1 & SFCF[7] = 1 FFFFh F000h EFFFh 4 KByte INTERNAL
(Block 1)
EA# = 1 & SFCF[7] = 0 FFFFh FFFFh
EA# = 0
32 KByte EXTERNAL 28 KByte EXTERNAL 64 KByte EXTERNAL
8000h 7FFFh
8000h 7FFFh
32 KByte INTERNAL
(Block 0)
32 KByte INTERNAL
(Block 0)
0000h
0000h
0000h
344 ILL F11.1
FIGURE 6: SST89C58 PROGRAM MEMORY ORGANIZATION Memory Re-mapping The SST89C54/58 memory re-mapping feature allows users to reorganize internal Flash memory sectors so that interrupts may be serviced when Block 0 of the internal Flash is being programmed. Since Block 0 occupies the low order program address space of the 8051 architecture where the interrupt vectors reside, those interrupt vectors will normally not be available when Block 0 is being programmed. SST89C54/58 provides four options of Memory Remapping (Refer to Table 2). When the lowest 4 KBytes are remapped, any program access within logical address range 0000h - 0FFFh will have the 4 most significant address bits forced to "1", redirecting the access to F000h - FFFFh. Note that the physical contents of the re-mapped portion of Block 0 (i.e. physical locations 0000h - 0FFFh in the current example) will not be accessible. Block 1 will still also be accessible through F000h - FFFFh. Figures 7 and 8 show re-mapped program memory organization for the SST89C54/58.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications Activation and Deactivation of Memory Re-mapping The actual amount of memory that is re-mapped is controlled by MAP_EN[1:0] bits as shown in Table 2. The MAP_EN[1:0] bits are the same bits as SFCF[1:0]. The MAP_EN[1:0] bits are under software control and can be changed during program execution. Since changing remapping will cause program re-location, it is advisable that the instruction that changes the MAP_EN[1:0] be in the portion of memory that is not affected by the remapping change. The MAP_EN[1:0] bits are initialized at Reset according to the contents of two non-volatile register bits, ReMap[1:0] (as shown in Table 2). The Re-Map[1:0] bits are programmed via PROG_RB1 and PROG_RB0 External Host Mode commands. Refer to External Host Programming Mode section for PROG_RB1 and PROG_RB0 commands. TABLE 2: RE-MAPPING TABLE Re-Map [1:0]1 11 10 01 00 MAP_EN2,3 00 01 10 11 Comments Re-mapping is turned off. Program memory is in normal configuration. 1 KByte of flash memory location is re-mapped. Program access to location 0000h-03FFh is redirected to F000h - F3FFh. 2 KBytes of flash memory location are re-mapped. Program access to location 0000h-07FFh is redirected to F000h - F7FFh. 4 KBytes of flash memory location is re-mapped. Program access to location 0000h-0FFFh is redirected to F000h - FFFFh. The contents of MAP_EN[1:0] are only updated according to Re-Map[1:0] on a successful reset. Any subsequent alteration to the Re-Map[1:0] bits will not automatically change the MAP_EN[1:0] bits without a reset. Similarly, changes to MAP_EN[1:0] during program execution will not change Re-Map[1:0] bits. To deactivate memory re-mapping, a CHIP-ERASE operation will revert Re-Map[1:0] to the default status of "11", disabling re-mapping. Programming 00b to SFCF[1:0] register also deactivates memory re-mapping. The effect of programming Re-Map[1:0] is available only after the next reset. Refer to In-Application Mode Commands section for more detailed information.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
344 PGM T2.3 1 Re-Map[1:0] are nonvolatile registers which are examined only during Reset. 2 MAP_EN[1:0] are initialized according to Re-Map[1:0] during Reset. 3 MAP_EN[1:0] are located in SFCF[1:0], they determine the Re-Mapping configuration. They may be changed by the program at run time.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications
EA# = 1 & SFCF[7] = 1 EA# = 1 & SFCF[7] = 0 SFCF [1:0] = 01/10/11 SFCF [1:0] = 01/10/11 FFFFh FFFFh 4 KByte INTERNAL (Block 1) F000h EFFFh 48 KByte EXTERNAL 44 KByte EXTERNAL
4000h 3FFFh
15/14/12 KByte INTERNAL
(Block 0)
4000h 3FFFh
15/14/12 KByte INTERNAL
(Block 0)
1/2/4 KByte INTERNAL 0000h
(Block 1)
1/2/4 KByte INTERNAL 0000h
(Block 1)
344 ILL F35.3
FIGURE 7: SST89C54 RE-MAPPED PROGRAM MEMORY ORGANIZATION
EA# = 1 & SFCF[7] = 1 EA# = 1 & SFCF[7] = 0 SFCF [1:0] = 01/10/11 SFCF [1:0] = 01/10/11 FFFFh FFFFh 4 KByte INTERNAL (Block 1) F000h EFFFh 32 KByte EXTERNAL 28 KByte EXTERNAL
8000h 7FFFh 31/30/28 KByte INTERNAL
(Block 0)
8000h 7FFFh 31/30/28 KByte INTERNAL
(Block 0)
1/2/4 KByte INTERNAL 0000h
(Block 1)
1/2/4 KByte INTERNAL 0000h
(Block 1)
344 ILL F36.1
FIGURE 8: SST89C58 RE-MAPPED PROGRAM MEMORY ORGANIZATION
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications Data Memory SST89C54/58 have 256 x 8 bits of on-chip RAM and can address up to 64 KBytes of external data memory. Special Function Registers (SFR) Most of the unique features of the FlashFlex51 microcontroller family are controlled by bits in special function registers (SFRs) located in the FlashFlex51 SFR Memory Map shown below. Individual descriptions of each SFR are provided and Reset values indicated in Tables 3A to 3E.
1 2 3
8 BYTES
F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80
B* ACC* PSW* T2CON* RCAP2L RCAP2H TL2 WDTC* IP* P3* SFCF SFCM SFAL SFAH IE* P2* SCON* SBUF P1* TCON* TMOD TL0 TL1 TH0 P0* SP DPL DPH
TH2
SFDT
SFST
TH1 WDTD PCON
FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87
4 5 6 7 8 9 10
FlashFlex51 SFR Memory Map
* = Bit Addressable SFRs All addresses are hexadecimal
344 ILL F23.1
SST89C54/58 Special Function Registers TABLE 3A: CPU RELATED SFRS
Symbol Description Accumulator B Register Program Status Word SP Stack Pointer DPL Data Pointer Low 0 DPH Data Pointer High 0 IE* Interrupt Enable IP* Interrupt Priority PCON Power Control * = Bit Addressable SFRs ACC* B* PSW* Direct Address E0h F0h D0h 81h 82h 83h A8h B8h 87h EA SMOD ET2 PT2 Bit Address, Symbol, or Alternative Port Function MSB ACC[7:0] B[7:0] RS1 RS0 SP[7:0] DPL[7:0] DPH[7:0] ES0 PS ET1 PT1 GF1 EX1 PX1 GF0 ET0 PT0 PD EX0 PX0 IDL RESET LSBValue 00h 00h 00h 07h 00h 00h 40h xx000000b 0xxx0000b
344 PGM T3A.3
11 12 13 14 15 16
CY
AC
F0
OV
F1
P
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications TABLE 3B: FLASH MEMORY PROGRAMMING SFRS
Symbol Description SFST SFCF SFCM SFDT SFAL SFAH SuperFlash Status SuperFlash Configuration SuperFlash Command SuperFlash Data SuperFlash Address Low SuperFlash Address High Direct Address B6h B1h B2h B5h B3h B4h Bit Address, Symbol, or Alternative Port Function MSB LSB SECD[2:0] BUSY Flash_busy VIS IAPEN MAP_EN FIE FCM RESET Value xxx00000b 000000xxb 00h 00h 00h 00h
344 PGM T3B.4
SuperFlash Data Register SuperFlash Low Order Byte Address Register - A7 to A0 (SFAL) SuperFlash High Order Byte Address Register - A15 to A8 (SFAH)
SuperFlash Status Register (SFST) (Read Only Register) Location 0B6h Symbol SECD2 SECD1 SECD0 BUSY 7 SECD2 6 SECD1 5 SECD0 4 - 3 Busy 2 Flash_busy 1 - 0 - Reset Value xxx00000b
Function Security bit 1. Security bit 2. Security bit 3. Please refer to Table 8 for security lock options. Burst-Program completion polling bit. 1: Device is busy with flash operation. 0: Device is available for next Burst-Program operation. Flash operation completion polling bit. 1: Device is busy with flash operation. 0: Device has fully completed the last command, including Burst-Program.
Flash_busy
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications SuperFlash Configuration Register (SFCF) Location 0B1h Symbol VIS 7 VIS 6 IAPEN 5 - 4 - 3 - 2 - 1 0 Reset Value 000000xxb MAP_EN1 MAP_EN0
1 2 3 4 5 6
Function Upper flash block visibility. 1: 4 KByte flash block visible from F000-FFFF. 0: 4 KByte flash block not visible. Enable IAP operation. 1: IAP commands are enabled. 0: IAP commands are disabled. Map enable bit 1. Map enable bit 0. MAP_EN[1:0] are initialized to default value according to Re-map [1:0] during Reset. Refer to Table 2.
IAPEN
MAP_EN1 MAP_EN0
SuperFlash Command Register (SFCM) Location 0B2h Symbol FIE 7 FIE 6 FCM6 5 FCM5 4 FCM4 3 FCM3 2 FCM2 1 FCM1 0 FCM0 Reset Value 00000000b
7 8 9 10 11 12 13 14 15 16
Function Flash Interrupt Enable. 1: INT1# is re-assigned to signal IAP operation completion. External INT1# interrupts are ignored. 0: INT1# is not reassigned. Flash operation command. 000_0001b Chip-Erase. 000_0110b Burst-Program. 000_1011b Sector-Erase. 000_1100b Byte-Verify. (1) 000_1101b Block-Erase. 000_1110b Byte-Program. All other combinations are not implemented, and reserved for future use.
(1)
FCM[6:0]
Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of FIE.
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications SuperFlash Data Register (SFDT) Location 0B5h Symbol SFDT 7 6 5 4 3 2 1 0 Reset Value 00000000b SuperFlash Data Register Function Mailbox register for interfacing with flash memory block (Data register).
SuperFlash Address Registers (SFAL) Location 0B3h 7 6 5 4 3 2 1 0 Reset Value 00000000b SuperFlash Low Order Byte Address Register
Symbol SFAL
Function Mailbox register for interfacing with flash memory block. (Low order address register).
SuperFlash Address Registers (SFAH) Location 0B4h Symbol SFAH 7 6 5 4 3 2 1 0 Reset Value 00000000b SuperFlash High Order Byte Address Register
Function Mailbox register for interfacing with flash memory block. (High order address register).
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications TABLE 3C: WATCHDOG TIMER SFRS
Watchdog Timer Control WDTD Watchdog Timer Data/Reload * = Bit Addressable SFRs WDTC* C0h 86h -
-
WDRE WDRL
WDTS
WDT
SWDT
X0h 00h
344 PGM T3C.1
1 2 3
Watchdog Timer Control Register (WDTC) Location 0C0h Symbol WDRE 7 - 6
-
5
-
4 -
3 WDRE
2 WDTS
1 WDT
0 SWDT
Reset Value 00000000b
4 5 6 7 8 9 10 11
Function Watchdog timer reset enable. 1: Enable watchdog timer reset. 2: Disable watchdog timer reset. Watchdog timer reset flag. 1: Hardware sets the flag on watchdog overflow. 0: External hardware reset clears the flag. Flag can also be cleared by writing a 1. Flag survives if chip reset happened because of watchdog timer overflow. Watchdog timer refresh. 1: Software sets the bit to force a watchdog timer refresh. 0: Hardware resets the bit when refresh is done. Start watchdog timer. 1: Start WDT. 0: Stop WDT.
WDTS
WDT
SWDT
Watchdog Timer Data/Reload Register (WDTD) Location 086h 7 6 5 4 3 2 1 0 Reset Value 00000000b Watchdog Timer Data/Reload
12 13 14 15 16
Symbol WDTD
Function Initial/Reload value in Watchdog Timer.
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications TABLE 3D: TIMER/COUNTERS SFRS
TMOD Timer/Counter Mode Control TCON* Timer/Counter Control TH0 Timer 0 MSB TL0 Timer 0 LSB TH1 Timer 1 MSB TL1 Timer 1 LSB T2CON* Timer / Counter 2 Control TH2 Timer 2 MSB TL2 Timer 2 LSB RCAP2H Timer 2 Capture MSB RCAP2L Timer 2 Capture LSB * = Bit Addressable SFRs 89h 88h 8Ch 8Ah 8Dh 8Bh C8h CDh CCh CBh CAh GATE TF1 C/T# TR1 Timer 1 M1 TF0 M0 TR0 GATE IE1 Timer 0 C/T# IT1 00h M1 IE0 M0 IT0 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
344 PGM T3D.0
TF2
EXF2
RCLK
TH0[7:0] TL0[7:0] TH1[7:0] TL1[7:0] TCLK EXEN2 TH2[7:0] TL2[7:0] RCAP2H[7:0] RCAP2L[7:0]
TR2
C/T2# CP/RL2#
TABLE 3E: INTERFACE SFRS
SBUF Serial Data Buffer SCON* Serial Port Control P0* Port 0 P1* Port 1 P2* Port 2 P3* Port 3 * = Bit Addressable SFRs 99h 98h 80h 90h A0h B0h SM0 RD# SM1 WR# SBUF[7:0] SM2 REN TB8 P0[7:0] P2[7:0] T1 T0 INT1#
Indeterminate
RB8
T1 T2 EX
R1 T2 RXD0
INT0#
TXD0
00h FFh FFh FFh FFh
344 PGM T3E.3
FLASH MEMORY PROGRAMMING The SST89C54/58 internal flash memory can be programmed or erased using the following two methods: * * External Host Mode (parallel only) In-Application Programming (IAP) Mode (parallel or serial)
entered by forcing PSEN# from a logic high to a logic low while RST input is being held continuously high. The SST89C54/58 will stay in External Host Mode as long as RST = 1 and PSEN# = 0. A READ-ID operation is necessary to "arm" the device, no other External Host Mode command can be enabled until a READ-ID is performed. In External Host Mode, the internal Flash memory blocks are accessed through the re-assigned I/O port pins (see Figure 9 for details) by an external host, such as an MCU programmer, PCB tester or a PC controlled development board.
EXTERNAL HOST PROGRAMMING MODE External Host Programming Mode provides the user with direct Flash memory access to program the Flash memory without using the CPU. External Host Mode is
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications When the chip is in the External Host Mode, Port 0 pins are assigned to be the parallel data input and output pins. Port 1 pins are assigned to be the non-multiplexed low order address bus signals for the internal flash memory (A7-A0). The first six bits of Port 2 pins (P2[5:0]) are assigned to be the non-multiplexed upper order address bus signals for the internal flash memory (A13-A8) along with two of the Port 3 pins (P3[5] as A15 and P3[4] as A14). Two upper order Port 2 pins (P2[7] and P2[6]) and two upper order Port 3 pins (P3[7] and P3[6]) along with RST, PSEN#, PROG#/ALE, EA# pins are assigned as the control signal pins. The Port 3 pin (P3[3]) is assigned to be the ready/busy status signal, which can be used for handshaking with the external host during a flash memory programming operation. The flash memory programming operation (Erase, Program, Verify, etc.) is internally self-timed. The insertion of an "arming" command prior to entering the External Host Mode by utilizing the "READ-ID" operation provides additional protection for inadvertent writes to the internal flash memory caused by a noisy or unstable system environment during power-up or brownout conditions. The External Host Mode uses twelve (12) hardware commands, which are decoded from the control signal pins, to facilitate the internal flash memory erase, program and verify processes. The External Host Mode is enabled on the falling edge of PSEN#. The External Host Mode Commands are enabled on the falling edge of ALE/ PROG#. The list in Table 4 outlines all the commands and the respective control signal assignment.
1 2 3 4 5 6
TABLE 4: EXTERNAL HOST MODE COMMANDS Operation READ-ID CHIP-ERASE BLOCK-ERASE SECTOR-ERASE BYTE-PROGRAM BURST-PROGRAM BYTE-VERIFY (Read) PROG-SB1 PROG-SB2 PROG-SB3 PROG-RB0 PROG-RB1 RST H H H H H H H H H H H H PSEN# L L L L L L L L L L L L PROG# EA# P3[7] P3[6] P2[7] P2[6] P0[7:0] P1[7:0] P3[5:4] /ALE P2[5:0] H
7 8 9 10 11 12 13 14 15 16
H H H H H H H H H H H H L L H H H L H H L L H H L L H L H H H H L H L L L L L H H H L H H L L L L H H H L L L H H H L H DO X X X DI DI DO X X X X X AL X X AL AL AL AL X X X X X AH X A[15:12] AH AH AH AH X X X X X
344 PGM T4.4

H
Note: Symbol signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations of the above input pins are invalid and may result in unexpected behaviors. Note: L = Logic low level; H = Logic high level; X = Don`t care; AL = Address low order byte; AH = Address high order byte; DI = Data Input; DO = Data Output; A[15:12] = 0xxxb for Block 0 and A[15:12} = "Fh" for Block 1.
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications
VSS VDD RST XTAL1 Port 0 XTAL2
0 6 7 0 0 1 2 Busy/Ready A14 A15 3 4 5 6 7 1 2
Input/ Output Data Bus
Port 2 Port 3
3 4 5 6 7 0
Address Bus A13-A8
Address Bus A15-A14
Flash Control Signals
Flash Control Signals Address Bus A7-A0
Port 1
6 7
EA#
ALE / PSEN# PROG#
344 ILL F01.1
FIGURE 9: I/O PIN ASSIGNMENTS FOR EXTERNAL HOST MODE Product Identification The READ-ID command accesses the Signature Bytes that identifies the device as an SST89C54/58 and the manufacturer as SST. External programmers primarily use these Signature Bytes, shown in Table 5, in the selection of programming algorithms. The Read-ID command is selected by the byte code of 00h on P2[7:6] and P3[7:6]. See Figure 10 for timing waveforms. TABLE 5: SIGNATURE BYTES TABLE Address Manufacturer's Code 30h SST89C54 Device Code 31h SST89C58 Device Code 31h programmed must be in the erased state prior to programming. Selection of the Erase command to use, prior to programming the device, will be dependent upon the contents already in the array and the desired field size to be programmed. The CHIP-ERASE command erases all bytes in both memory blocks (Block 0 and Block 1) of the SST89C54/ 58. This command ignores the Security Lock status and will erase the Security bits and the Re-Map bits. The CHIP-ERASE command is selected by the binary code of 00b on P3[7:6] and 01b on P2[7:6]. See Figure 11 for timing waveforms. The BLOCK-ERASE command erases all bytes in one of the memory blocks (16/32K or 4K) of the SST89C54/58. This command will not be enabled if the security lock is enabled on the selected memory block. The selection of the memory block to be erased is determined by A[15:12] (P3[5], P3[4], P2[5], P1[4]). If A15 is a "0", then the primary flash memory Block 0 (16/32K), is selected. If A[15:12] = "Fh", then the secondary flash memory Block 1 (4K) is selected. The BLOCK-ERASE command is selected by the binary code of 11b on P3[7:6] and 01b on P2[7:6]. See Figure 12 for the timing waveforms. The SECTOR-ERASE command erases all of the bytes in a sector. The sector size for the primary flash memory (Addresses 0000h-3FFFh/7FFFh) is 128 Bytes. The sector size for the secondary flash memory (Addresses F000h-FFFFh) is 64 bytes. This command will not be executed if the Security lock is enabled on the selected memory block. The selection of the memory sector to be erased is determined by P1[7:6] (A7 & A6), P2[5:0] (A13A8) and P3[5:4] (A15 & A14). The SECTOR-ERASE command is selected by the binary code of 10b on P3[7:6] and 11b on P2[7:6]. See Figure 13 for timing waveforms.
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Data BFh E4h E2h
344 GPM T5.1
External Host Mode Commands The twelve SST89C54/58 External Host Mode Commands are READ-ID, CHIP-ERASE, BLOCK-ERASE SECTOR-ERASE, BYTE-PROGRAM, BURST-PROGRAM, BYTE-VERIFY, PROG-SB1, PROG-SB2, PROG-SB3, PROG-RB0 and PROG-RB1. See Table 4 for all signal logic assignments and Table 7 for all timing parameter values for the External Host Mode Commands. The critical timing for all Erase and Program commands, is self-generated by the on-chip flash memory controller. The high-to-low transition of the PROG# signal initiates the Erase and Program commands, which are synchronized internally. The Read commands are asynchronous reads, independent of the PROG# signal level. The following three commands are used for erasing all or part of the memory array. All the data in the memory array will be erased to FFh. Memory locations that are to be
(c) 2000 Silicon Storage Technology, Inc.
FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications The BYTE-PROGRAM and BURST-PROGRAM commands are used for programming new data into the memory array. Selection of which Program command to use will be dependent upon the desired programming field size. Programming will not take place if any security locks are enabled on the selected memory block. The BYTE-PROGRAM command programs data into a single byte. Ports P0[7:0] are used for data in. The memory location is selected by P1[7:0], P2[5:0], and P3[5:4] (A15-A0). The BYTE-PROGRAM command is selected by the binary code of 11b on P3[7:6] and 10b on P2[7:6]. See Figure 14 for timing waveforms. The BURST-PROGRAM command programs data to an entire row, sequentially byte-by-byte. Ports P0[7:0] are used for data in. The memory location is selected by P1[7:0], P2[5:0], and P3[5:4] (A15-A0). The BURSTPROGRAM command is selected by the binary code of 01b on P3[7:6] and 10b on P2[7:6]. See Figure 15 for timing waveforms. The BYTE-VERIFY command allows the user to verify that the SST89C54/58 correctly performed an Erase or Program command. Ports P0[7:0] are used for data out. The memory location is selected by P1[7:0], P2[5:0], and P3[5:4] (A15-A0). The BYTE-VERIFY command is selected by the binary code of 11b on P3[7:6] and 00b on P2[7:6]. This command will be disabled if any security locks are enabled on the selected memory block. See Figure 16 for timing waveforms. The PROG-SB1, PROG-SB2, PROG-SB3 commands program the security bits, the functions of these bits are described in a Security Lock section and also in Table 8. Once programmed, these bits can only be cleared through a CHIP-ERASE command. The PROG-RB1, and PROG-RB0 commands program the Re-Map[1:0] bits. The Re-Map[1:0] bits determine the Memory Re-mapping default option on reset. Upon completion of the Reset sequence, the MAP_EN[1:0] bits are initialized to the default value set by the ReMap[1:0] bits according to Table 2. Subsequent program manipulation of MAP_EN[1:0] bits will alter the Memory Re-mapping option but will not change the Re-Map[1:0] bits. Therefore, any changes to MAP_EN[1:0], without corresponding updates to Re-Map[1:0], will not survive a Reset cycle. If an External Host Mode command, except for CHIPERASE, is issued to a locked memory block, the device will ignore this command. External Host Mode Clock Source In External Host Mode, an internal oscillator will provide clocking for the SST89C54/58. The on-chip oscillator will
(c) 2000 Silicon Storage Technology, Inc.
be turned on as the SST89C54/58 enters External Host Mode; i.e. when PSEN# goes low while RST is high. The oscillator provides both clocking for the Flash Control Unit as well as timing references for Program and Erase operations. During External Host Mode, the CPU core is held in reset. Upon exit from External Host Mode, the internal oscillator is turned off. The same oscillator also provides the time base for the watchdog timer and timing references for IAP Mode Program and Erase operations. See more detailed description in later sections. Arming Command An arming command sequence must take place before any External Host Mode sequence command is recognized by the SST89C54/58. This prevents accidental triggering of External Host Mode Commands due to noise or programmer error. The arming command is as follows: 1. PSEN# goes low while RST is high. This will get the machine in External Host Mode, re-configuring the pins. 2. A Read-ID command is issued and held for 1 ms. After the above sequence, all other External Host Mode commands are enabled. Before the Read-ID command is received, all other External Host commands received are ignored. Programming a SST89C54/58 To program data into the memory array, apply power supply voltage (VDD) to VDD and RST pins, and perform the following steps: 1. Maintain RST high and toggle PSEN# from logic high to low, in sequence per the appropriate timing diagram. 2. Raise EA# High (either VIH or VH). 3. Issue READ-ID command to enable the External Host Mode. 4. Verify that the memory blocks or sectors for programming is in the erased state, FFh. If they are not erased, then erase them using the appropriate Erase command. 5. Select the memory location using the address lines (P1[7:0], P2[5:0], P3[5:4]). 6. Present the data in on P0[7:0]. 7. Pulse ALE/PROG#, observing minimum pulse width. 8. Wait for low to high transition on READY/BUSY# (P3[3]). 9. Repeat steps 5 - 8 until programming is finished. 10. Verify the flash memory contents.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications Flash Operation Status Detection (Ext. Host Handshake) The SST89C54/58 provide two firmware means for an external host to detect the completion of a flash memory operation to optimize the Program or Erase time. The end of a flash memory operation cycle (Erase or Program) can be detected by: 1) monitoring the Ready/ Busy# bit at P3[3]; 2) monitoring the Data# Polling bit at P0[7] and P0[3]. Ready/Busy# (P3[3]) The progress of the flash memory programming can be monitored by the Ready/Busy# output signal. P3[3] is driven low, some time after ALE/PROG# goes low during a flash memory operation to indicate the Busy# status of the Flash Control Unit (FCU). P3[3] is driven high when the Flash programming operation is completed to indicate the Ready status. During a Burst-Program operation, P3[3] is driven high (Ready) in between each byte-programmed among the burst to indicate the ready status to receive the next byte. When the external host detects the Ready status after a byte among the burst is programmed, it shall then put the data/address (within the same page) of the next byte on the bus and drive ALE/PROG# low (pulse), before the time-out limit expires. See Table 7 for details. BurstProgram command presented after time-out will wait until next cycle. Therefore, it will have longer programming time. Data# Polling (P0[7] & P0[3] During a Program operation, any attempts to read (ByteVerify), while the device is busy, will receive the complement of the data of the last byte loaded (logic low, i.e. "0" for an erase) on P0[3] and P0[7] with the rest of the bits "0". During a Program operation, the Byte-Verify command is reading the data of the last byte loaded, not the data at the address specified. The true data will be read from P0[7], when the device completes each byte programmed among the burst to indicate the Ready status to receive the next byte. When the external host detects the Ready status after a byte among the burst is programmed, it should then put the data/address (in the same page) of the next byte on the bus and drive ALE/PROG# low immediately, before the time-out limit expires (See programming time spec. in Table 7 for details.). The true data will be read from P0[3], when the Burst-Program command is terminated and the device is ready for the next operation. The termination of the Burst-Program can be accomplished by: 1) Change to a new X-Addresses (Note: the X-Address range are different for the 4Kx8 flash Block 1 and for the 16/32K x 8 flash Block 0.); 2) Change to a new command that requires a high to low transition of the ALE/ PROG# (i.e. any Erase or Program command); 3) Wait for time out limit expires (20 s); when programming the next byte.
Flash Memory Programming with External Host Mode (Figures 10-16)
TSU
RST
TES
PSEN# ALE/PROG# EA#
P2[7:6] ,P3[7:6] P3[5:4] ,P2[5:0] ,P1 P0
TRD 0000b 0030h BFh
TRD 0000b 0031h E4h/E2h
344 ILL F02.5
FIGURE 10: READ-ID
Read chip signature and identification registers at the addressed location.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications
TSU RST TES PSEN# TADS ALE/PROG# TPROG EA# TCE P3[3] TDH
1 2 3 4 5
0001b
P3[7:6], P2[7:6]
6
344 ILL F03.4
7
FIGURE 11: CHIP-ERASE
Erase both flash memory blocks. Security lock is ignored and the security bits are erased too.
8 9
TSU RST TES
10 11
TPROG TDH
PSEN#
TADS ALE/PROG#
EA# TBE P3[3]
12 13 14
344 ILL F04.5
P3[7:6], P2[7:6] P3[5:4], P2[5:0]
1101b AH
15 16
FIGURE 12: BLOCK-ERASE
Erase one of the flash memory blocks, if the security lock is not activated on that flash memory block. The highest address bits A[15:12] determines which block is erased. For example, if A15 is "0", primary flash memory block is erased. If A[15:12] = "Fh", the secondary block is erased.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications
TSU RST TES
PSEN#
TADS ALE/PROG# TPROG EA# P3[3] TSE P3[7:6], P2[7:6] P3[5:4], P2[5:0] P1 1011b AH AL
344 ILL F05.4
TDH
FIGURE 13: SECTOR-ERASE
Erase the addressed sector if the security lock is not activated on that flash memory block.
TSU RST TES PSEN# TADS ALE/PROG# TPROG EA# P3[3] TPB P3[5:4], P2[5:0] P1 P0 P3[7:6], P2[7:6]
* See Table 4 for control signal assignments for PROG-SBx and PROG-RBx.
TDH
AH AL DI 1110b*
344 ILL F06.6
FIGURE 14: BYTE-PROGRAM; PROG-SB3, PROG-SB2, PROG-SB1, PROG-RB1 AND PROG-RB0
Program the addressed code byte if the byte location has been successfully erased and not yet programmed. ByteProgram operation is only allowed when the security lock is not activated on that flash memory block.
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications
TSU RST TES PSEN# TADS ALE/PROG# TPROG EA# P3[3] TBUP1 row address byte address P0 P3[7:6], P2[7:6] 16K/32K Block 4K Block row address byte address DI 0110b row address = A15: A6; byte address = A5:A0 row address = A15: A5; byte address = A4:A0
344 ILL F07.4
1 2
TDH TDH TDH
3
TBUPRCV
TBUP
TBUP
4 5 6 7 8 9
row address byte address DI byte address DI
FIGURE 15: BURST-PROGRAM
Program the entire addressed row by burst programming each byte sequentially within the row if the byte location has been successfully erased and not yet programmed. This operation is only allowed when the security lock is not activated on that flash memory block.
TSU
RST PSEN# ALE/PROG# EA#
TES
10 11 12
TOA 1100b TAHA
P3[7:6], P2[7:6]
13 14
P0 P1 P3[5:4], P2[5:0]
FIGURE 16: BYTE-VERIFY
AL
DO TALA
15
AH
344 ILL F08.3
16
Read the code byte from the addressed flash memory location if the security lock is not activated on that flash memory block.
(c) 2000 Silicon Storage Technology, Inc. 344-2 8/00
25
FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications IN-APPLICATION PROGRAMMING MODE The SST89C54/58 offers 20/36 KByte of In-Application Programmable flash memory. During In-Application Programming, the CPU of the microcontroller enters IAP Mode. The two blocks of flash memory allows the CPU to concurrently execute user code from one block, while the other is being reprogrammed. The CPU may also fetch code from an external memory while all internal flash is being reprogrammed. The chip can start the InApplication Programming operation either with the external program code execution being enabled (EA# = L) or disabled (EA#=H). The mailbox registers (SFST, SFCM, SFAL, SFAH, SFDT and SFCF) located in the Special Function Register (SFR), control and monitor the device's erase and program process. Table 6 outlines the commands and their associated settings of the mailbox registers. In-Application Programming Mode Clock Source During IAP Mode, both the CPU core and the flash controller unit are driven off the external clock. However, an internal oscillator will provide timing references for Program and Erase operations. The duration of Program and Erase operations will be identical between External Host Mode and In-Application Mode. The internal oscillator is only turned on when required, and is turned off as soon as the Flash operations complete. IAP Enable Bit The IAP Enable Bit, SFCF[6], initializes In-Application Programming mode, enabling IAP command decoding. Until this bit is set all flash programming IAP commands will be ignored. In-Application Programming Mode Commands All of the following commands can only be initiated in the IAP Mode. In all situations, writing the control byte to the (SFCM) register will initiate all of the operations. All commands (except CHIP-ERASE) will not be enabled if the security features are enabled on the selected memory block. The critical timing for all Erase and Program commands, is self-generated by the on-chip flash controller unit. The two Program commands are for programming new data into the memory array. The portion of the memory array to be programmed should be in the erased state, FFh. If the memory is not erased, then erase it with an appropriate Erase command. Warning: Do not write (program or erase) to a block that the code is currently fetching from. This will cause unpredictable program behavior and may corrupt program data. The CHIP-ERASE command erases all bytes in both memory blocks (16/32K and 4K). This command ignores the Security Lock status and will erase the security lock bits and Re-Map bits. The CHIP-ERASE command sequence is as follows:
IAP Enable ORL SFCF, #40h Set-Up MOV SFDT, #55h
Polling scheme MOV SFCM, #01h
Interrupt scheme MOV SFCM, #81h
SFST[2] indicates operation completion
INT1# occurrence indicates completion
344 ILL F39.2
The BLOCK-ERASE command erases all bytes in one of the two memory blocks (16/32K or 4K). The selection of the memory block to be erased is determined by the "A15" bit (SFAH[7]) of the SuperFlash Address Register. If SFAH[7] = 0b, the primary flash memory Block 0 is selected (16/32K). If SFAH[7:4] = Fh, the secondary flash memory Block 1 is selected (4K). The BLOCKERASE command sequence is as follows:
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications The 16/32 KByte memory contains 128/256 uniform sectors of 128 Bytes each. The 4 KByte memory contains 64 uniform sectors of 64 Bytes each. The selection of the sector to be erased is determined by the contents of SFAH, SFAL. Please refer to Figure 4 for an illustration of memory sector organization. The BYTE-PROGRAM command programs data into a single byte. The BYTE-PROGRAM command sequence is as follows:
IAP Enable
1 2 3 4
Erase 32 KBlock MOV SFAH, #00h
OR
Erase 4 KBlock MOV SFAH, #F0h
Set-Up MOV SFDT, #55h
IAP Enable
Polling scheme MOV SFCM, #0Dh Interrupt scheme MOV SFCM, #8Dh
5
Program byte address MOV SFAH, #byte_addressh MOV SFAL, #byte_addressl
SFST[2] indicates operation completion
INT1# occurrence indicates completion
344 ILL F40.5
6 7 8
Move data to SFDT MOV SFDT, #data
The SECTOR-ERASE command erases all of the bytes in a sector. The sector size for the primary flash memory Block 0 (Addresses 0000h-3FFFh/7FFFh) is 128 Bytes. The sector size for the secondary flash memory Block 1 (Address F000h-FFFFh) is 64 Bytes. The SECTORERASE command sequence is as follows:
Polling scheme MOV SFCM, #0Eh
Interrupt scheme MOV SFCM, #8Eh
9 10 11
SFST[2] indicates operation completion
IAP Enable
INT1# occurrence indicates completion
344 ILL F42.3
Program sector address MOV SFAH, #sector_addressh MOV SFAL, #sector_addressl
Polling scheme MOV SFCM, #0Bh
Interrupt scheme MOV SFCM, #8Bh
The BURST-PROGRAM command programs data into half of a sector (row) which has the same row address, sequentially byte-by-byte. Refer to the Memory Organization section and Figures 4 and 15 for details. The MOVC command and all IAP commands except BURSTPROGRAM are invalid during the BURST-PROGRAM cycle. The BURST-PROGRAM command sequence is as follows:
12 13 14 15 16
SFST[2] indicates operation completion
INT1# occurrence indicates completion
344 ILL F41.3
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Preliminary Specifications PROG-SB3, PROG-SB2, PROG-SB1 commands are used to program the Security bits (see Table 8). These commands work similarly to a BYTE-PROGRAM command, except no address and data is specified. Upon completion of any of those commands, the security options will be updated immediately. Security bits previously in un-programmed state can be programmed by these commands. The PROG-SB3, PROG-SB2, PROG-SB1 sequences are as follows:
IAP Enable
Program byte address MOV SFAH, #byte_addressh MOV SFAL, #byte_addressl
Move data to SFDT MOV SFDT, #data
IAP Enable
Polling scheme MOV SFCM, #06h
Interrupt scheme MOV SFCM, #86h
Set-Up MOV SFDT, #55h
Next same row address
SFST[3] indicates byte completion
INT1# occurrence indicates completion
Y
Program another byte N
Program sb1 MOV SFCM, #0Fh OR or MOV SFCM, #8Fh
Program sb2 MOV SFCM, #03h or MOV SFCM, #83h
OR
Program sb3 MOV SFCM, #05h or MOV SFCM, #85h
Polling SFST[2] indicates completion
Interrupt INT1# occurrence completion
344 ILL F45.3
SFST[2] indicates Burst-Program completion
344 ILL F43.5
The BYTE-VERIFY command allows the user to verify that the SST89C54/58 has correctly performed an Erase or Program command. The BYTE-VERIFY command sequence is as follows:
IAP Enable
PROG-RB1, PROG-RB0 commands are used to program the Re-Map[1:0] bits (see Table 2). These commands work similarly to a BYTE-PROGRAM command except no address and data is needed. These commands only change the Re-Map[1:0] bits and have no effect on MAP_EN[1:0] until after a reset cycle. Therefore, the effect of these commands is not immediate.
Program byte address MOV SFAH, #byte_addressh MOV SFAL, #byte_addressl
MOV SFCM, #0Ch
SFDT register contains data
344 ILL F44.2
BYTE-VERIFY command returns the data byte in SFDT if the command is successful. The user is required to check that the previous Flash operation has fully completed before issuing a BYTE-VERIFY.
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Preliminary Specifications Re-Map bits previously in un-programmed state can be programmed by these commands. The PROG-RB1, PROG-RB0 sequences are as follows: Polling A command that uses the polling method to detect flash operation completion should poll on the Flash_Busy bit (SFST[2]). When Flash_Busy de-asserts (logic 0), the device is ready for the next operation. The BUSY bit (SFST[3]) is provided for Burst-Program. In between bytes within a burst sequence, the Busy bit will become logic 0 to indicate that the next BurstProgram byte should be presented. Completion of the full burst cycle is indicated also by Flash_Busy bit (SFST[2]). MOVC instruction may also be used for verification of the Programming and Erase operation of the flash memory. MOVC command will fail if it is directed at a flash block that is still busy.
1 2 3 4 5 6
IAP Enable
Set-Up MOV SFDT, #55h
Program Re-Map [0] MOV SFCM, #08h or MOV SFCM, #88h
Program Re-Map [1] MOV SFCM, #09h or MOV SFCM, #89h
Polling SFST[2] indicates completion
OR
Interrupt INT1# occurrence completion
344 ILL F46.4
7 8 9 10 11 12 13 14 15 16
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Preliminary Specifications Interrupt Termination If interrupt termination is selected, (SFCM[7] is set), then an interrupt (INT1) will be generated to indicate flash operation completion. Under this condition, the INT1 becomes an internal interrupt source. The INT1# pin can now be used as a general purpose port pin, and it cannot be a source of External Interrupt 1. TABLE 6: IN-APPLICATION PROGRAMMING MODE COMMANDS Operation CHIP-ERASE BLOCK-ERASE SECTOR-ERASE BYTE-PROGRAM BURST-PROGRAM BYTE-VERIFY (Read)
Notes:
For an interrupt to occur, appropriate interrupt enable bits must be set. EX1 and EA bits of IE register must be set. The TCON[2] (IT1) bit of TCON register must also be set for edge trigger detection.
SFAH [7:0] X AH2 AH AH AH AH
SFAL [7:0] X X AL AL AL AL
SFDT [7:0] 55h 55h X DI DI DO
SFCM [6:0]1 01h 0Dh 0Bh 0Eh 06h 0Ch
344 PGM T6.3
X = Don't Care; AL = Address low order byte; AH = Address high order byte; DI = Data Input; DO = Data Output All other values are in hex 1 Interrupt/Polling enable for flash operation completion SFCM[7] = 1: Interrupt enable for flash operation completion 0: polling enable for flash operation completion 2 SFAH[7] = 0: Selects Block 0: SFAH[7:4] = Fh selects Block 1
TABLE 7: FLASH MEMORY PROGRAMMING/VERIFICATION PARAMETERS Parameter1,2 Reset Setup Time Read-ID Command Width PSEN# Setup Time Address, Command, Data Setup Time Chip-Erase Time Block-Erase Time Sector-Erase Time Program Setup Time Address, Command, Data Hold Byte-Program Time 3 Verify Command Delay Time Verify High Order Address Delay Time Verify Low Order Address Delay Time First Burst-Program Byte Time4 Burst-Program Time 3,4 Burst-Program Recovery4 Burst-Program Time-Out Limit
Symbol TSU TRD TES TADS TCE TBE TSE TPROG TDH TPB TOA TAHA TALA TBUP1 TBUP TBUPRCV TBUPTO
Min 3 1 1.125 0
Max
1.1 1.2 0
11.7 9.4 2.3
31 20
110 50 50 50 85 45 110
Units s s s ns ms ms ms s ns s ns ns ns s s s s
344 PGM T7.4
Note: 1. Program and Erase times will scale inversely relative to programming clock frequency. 2. All timing measurements are from the 50% of the input to 50% of the output. 3. Each byte must be erased before program. 4. External Host Mode only.
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Preliminary Specifications
Accessing Internal Memory (EA# = 0)
VSS VDD RST XTAL1 Port 0 XTAL2
RXD TXD INT0# INT1# T0 T1 WR# RD# 0 1 2 3 4 5 6 7 0 6 7 0 1 2
Accessing External Memory (EA# = 1)
VSS VDD RST
Address and Data Bus T2 T2EX
XTAL1 Port 0 XTAL2
RXD TXD INT0# INT1# T0 T1 WR# 0 1 2 3 4 5 6 7
0 6 7 0 1 2
General Purpose I/O T2 T2EX
1 2 3 4
Port 1 Port 3
3 4 5 6 7 0
Port 1 Port 3
3 4 5 6 7 0
Port 2
6 7
Address Bus
RD#
Port 2
6 7
General Purpose I/O
5 6 7 8 9 10 11 12 13 14 15 16
EA#
ALE / PSEN# PROG#
EA#
ALE / PSEN# PROG#
344 ILL F09.1
FIGURE 17: IN-APPLICATION PROGRAMMING MODE I/O ASSIGNMENT TIMERS/COUNTERS The SST89C54/58 have three 16-bit registers that can be used as either timers or event counters. The three Timers/Counters are the Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2) registers. These three registers are located in the SFR as pairs of 8-bit registers. The low byte of the T0 register is stored in the Timer 0 LSB (TL0) special function register and the high byte of the T0 register is stored in the Timer 0 MSB (TH0) special function register. The low byte of the T1 register is stored in the Timer LSB (Tl1) special function register and the high byte of the T1 register is stored in the Timer 1 MSB (TH1) special function register. The low byte of the T2 register is stored in the Timer 2 LSB (TL2) special function register and the high byte of the T2 register is stored in the Timer 2 MSB (TH2) special function register. SERIAL I/O (UART) The SST89C54/58 Serial I/O ports is a full duplex port that allows data to be transmitted and received simultaneously in hardware by the transmit and receive registers, respectively, while the software is performing other tasks. The Serial I/O port performs the function of an UART (Universal Asynchronous Receiver/Transmitter) chip. The transmit and receive registers are both located in the Serial Data Buffer (SBUF special function register. Writing to the SBUF register loads the transmit register, and reading from the SBUF register obtains the contents of the receive registers. The Serial I/O port has four modes of operation which are selected by the Serial Port Mode Specifier (SM0 and SM1) bits of the Serial Port Control (SCON) special function register. In all four modes, transmission is initiated by any instruction that uses the SBUF register as a destination register. Reception is initiated in mode 0 when the Receive Interrupt (RI) flag bit of the Serial Port Control (SCON) special function register is cleared and the Reception Enable/ Disable (REN) bit of the SCON register is set. Reception is initiated in the other modes by the incoming start bit if the REN bit of the SCON register is set.
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Preliminary Specifications WATCHDOG TIMER The SST89C54/58 offer an enhanced programmable Watchdog Timer (WDT) for fail safe protection against software deadlock and allows an automatic recovery. To protect the system against software deadlock, the user has to refresh the WDT within a user defined time period. If the software fails to do this periodical refresh, an internal hardware reset will be initiated. The software can be designed such that the WDT times out if the program does not work properly. It also times out if a software error is based on the hardware related problems. The WDT in the SST89C54/58 share the same time base with the flash controller unit. When the flash controller unit is operating, the time base will be re-started by the hardware periodically, therefore delaying the time-out period of the watchdog timer. The upper 8-bits of the time base register are used as the reload register of the WDT. The internal oscillator that drives the WDT operates within a frequency range as shown in Table 11. Minimum clock cycle for the WDT is 7.7ms. Figure 18 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control watchdog timer operation. During idle mode, WDT operation is temporarily suspended, and resumes upon an interrupt exit from idle.
CLK
Counter
7.7 ms min. WDT Upper Byte
WDT Reset
Internal Reset
Ext. RST
WDTC
WDTD
344 ILL F10.2
FIGURE 18: BLOCK DIAGRAM OF PROGRAMMABLE WATCHDOG TIMER SECURITY LOCK The Security feature protects against software piracy and prevents the contents of the flash from being read by unauthorized parties. It also protects against code corruption resulting from accidental erasing and programming to the internal flash memory locations. There are two different types of security locks in the SST89C54/58 security lock system: Hard Lock and SoftLock. Hard Lock When the Hard Lock is activated, the MOVC instructions executed from Un-Locked or SoftLocked program address space, are disabled from reading code bytes in Hard Locked memory blocks (See Table 9). The Hard Lock can either lock both flash memory blocks or just lock the upper flash memory block (Block 1). All External Host and IAP commands except for CHIP-ERASE are ignored for the Hard Locked memory blocks. SoftLock SoftLock allows flash contents to be altered under a secure environment. This lock option allows the user to update program code in the Soft Locked memory block through InApplication Programming Mode under a predetermined secure environment. For example, if the Block 1 (4K) memory block is locked, and the Block 0 (16K/32K) memory block is Soft Locked, code residing in Block 1 can program Block 0. The following IAP mode commands issued through the command mailbox register, SFCM, executed from a Hard Locked block can be operated on a Soft Locked block: BLOCK-ERASE, SECTOR-ERASE, BYTE-PROGRAM, BURST-PROGRAM and BYTEVERIFY. In External Host Mode, SoftLock behaves the same as a Hard Lock.
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Preliminary Specifications STATUS OF THE SECURITY LOCK The three bits that indicate the SST89C54/58 security lock status are located in SFST[7:5]. As shown in Figure 19 and Table 8, the three security lock bits control the lock status of the primary and secondary blocks of memory. There are four distinct levels of security lock status. In the first level, none of the security lock bits are programmed and both blocks are unlocked. In the second level, although, both blocks are now locked and cannot be written, they are available for read operation via Byte-Verify. In the third level, three different options are available: Block 1 Hard Lock / Block 0 SoftLock, SoftLock on both blocks, and Hard Lock on both blocks. Locking both blocks is the same as Level 2 except read operation isn't available. The fourth level of security is the most secure level operation. It doesn't allow read/write of internal memory or boot from external memory. Please note that for unused combinations of the security lock bit the chip will default to Level 4 status.
1 2 3 4 5 6
UUU/NN
Level 1 Level 2
PUU/LL
UPU/SS
UUP/LS
Level 3
PPU/LL = PUP/LL
7
Level 4
344 ILL F38.1
PPP/LL
8 9 10
Notes: 1. P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1), N = Not Locked, L = Hard Locked, S = SoftLocked
FIGURE 19: SECURITY LOCK LEVELS TABLE 8: SECURITY LOCK OPTIONS Security Lock Bits Level SFST[7:5] 11 21 1 000 U U 2 100 P U 31 U U Security Status of: Security Type Block 1 Block 0 Unlock Unlock No Security Features are Enabled. Hard Lock Hard Lock MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA# is sampled and latched on Reset, and further programming of the flash is disabled. Hard Lock Hard Lock Level 2 plus Verify disabled, both blocks locked. Level 2 plus verify disable. code in Block 1 can program Block 0 and vice versa. Hard Lock SoftLock Level 2 plus verify disabled, code in Block 1 can program Block 0. Hard Lock Hard Lock Same as Level 3, but external boot is disabled.
344 PGM T8.4
11 12 13 14 15 16
3
110 101 010 001
P P U U P
P U P U P
U P U P P
SoftLock
SoftLock
4
111
Notes: 1 1, 2, and 3, respectively, refer to the first, second, and third security lock bits. 2 P = Programmed (Cell logic state = 0), U = Unprogrammed (Cell logic state = 1). 3 SFST[7:5] = Security Lock Decoding Bits (SECD) 4 All unused combinations default to level 4, "PPP".
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Preliminary Specifications TABLE 9: MOVC ACCESS WITH SECURITY LOCK ACTIVATED SFST[7:5] 011/100/101/110/111 (Hard Lock on both blocks) 001 (Block 0 = SoftLock Block 1 = Hard Lock) MOVC Address1 Block 0/1 External Memory Target Address2 Any Location Block 0/1 External Block 0 Block 1 External Any Location Block 0/1 External Any Location Block 0/1 External Any Location MOVC allowed3 Y N Y Y N Y Y N Y Y N Y Y
344 PGM T9.3
Block 0 Block 1 External Block 0/1 External Any Location
010 (SoftLock on both blocks) 000
Notes: 1 Location of MOVC instruction 2 Target Address is the location of the instruction being read 3 Y = Indicates MOVC instruction is allowed; N = Indicates MOVC instruction is not allowed;
RESET A system reset initializes the MCU and begins program execution at program memory location 0000h. The reset input for the SST89C54/58 is the RST pin. In order to reset the SST89C54/58, a logic level high must be applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable. ALE, PSEN# are weakly pulled high during reset. During reset, ALE and PSEN# output a high level in order to perform correct reset. This level must not be affected by external element. A system reset will not affect the 256 Bytes of on-chip RAM while the SST89C54/58 is running, however, the contents of the on-chip RAM during power up are indeterminate. All Special Function Registers (SFR) return to their reset values, which are outlined in Tables 3A to 3E. Power-On Reset At initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algorithm has written one's to all the pins. Powering up the device without a valid reset could cause the CPU to start executing instructions from an indeterminate location. Such undefined states may inadvertently corrupt the code in the flash. When power is applied to the SST89C54/58, the RST pin must be held long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid PowerOn Reset. An example of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10F capacitor and to VSS through an 8.2KW resistor as shown in Figure 20. Note that if an RC circuit is being used, provisions should be made to ensure the VDD rise time does not exceed 1 millisecond and the oscillator start-up time does not exceed 10 milliseconds. For a low frequency oscillator with slow start-up time the reset signal must be extended in order to account for the slow start-up time. This method maintains the necessary relationship between VDD and RST to avoid programming at an indeterminate location, which may cause corruption in the code of the flash. For more information on system level design techniques, please review Design Considerations for the SST FlashFlex51 Family Microcontroller Application Note.
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Preliminary Specifications POWER-SAVING MODES The SST89C54/58 provides three power saving modes of operation for applications where power consumption is critical. The three power saving modes are: Idle, Power Down and Standby (Stop Clock). Idle Idle mode is entered by a software command which sets the IDL bit in the PCON register. In Idle mode the program counter (PC) is stopped. The system clock continues to run and all interrupts and peripheral functions (timers/counters, serial port, etc.) are active. In this mode the power dissipation is approximately 25% of the fully active device. The SST89C54/58 exits Idle mode through either a system interrupt or a hardware reset. The interrupt clears the IDL bit and the program resumes execution beginning at the instruction immediately following the one which invoked the Idle mode. A hardware reset starts the device similar to power-on reset. Power Down The Power Down mode is also entered by a software command which sets the PD bit in the PCON register. In Power Down mode, the clock is stopped and external interrupts are active for level sensitive interrupt only. Power Down mode reduces the current dissipation to 15A, typical. The SST89C54/58 exits Power Down mode through either an enabled external level sensitive interrupt or a hardware reset. The interrupt clears the PD bit and the program resumes execution beginning at the instruction immediately following the one which invoked the Power Down mode. A hardware reset starts the device similar to power-on reset. Standby (Stop Clock) Standby mode is similar to Power Down mode, except that Power Down mode is initiated by a software command and Standby mode is initiated by external hardware gating off the external clock to the SST89C54/58 device. The current dissipation is reduced to 15A, typical. The on-chip SRAM and SFR data are maintained in Standby mode. The device resumes operation at the next instruction when the clock is reapplied to the part. Table 10 outlines the different power-saving modes, including entry and exit procedures and MCU functionality.
1 2 3 4 5 6 7 8 9 10
VDD + 10F RST 8.2K SST89C54/58 C2 XTAL2
12MHz
11
VDD
12 13
XTAL1 C1
14 15
344 ILL F31.1
FIGURE 20: POWER-ON RESET CIRCUIT
16
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Preliminary Specifications TABLE 10: SST89C54/58 POWER SAVING MODES Mode
Idle Mode
Initiated by
Software (Set IDL bit in PCON)
Current Drain
25% of IDD level when device is fully active
State of MCU
CLK is running. Interrupts, serial port and timers/counters are active. Program Counter is stopped. ALE and PSEN# signals at a HIGH level during Idle. All registers remain unchanged.
Exited by
Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits Idle mode, after the ISR RETI instruction program resumes execution beginning at the instruction following the one that invoked Idle mode. If needed in a specific application, a user could consider placing two or three NOP instructions after the instruction that invokes idle mode to eliminate any problems. A hardware reset restarts the device similar to a power-on reset. Enabled external level sensitive interrupt or hardware reset. Start of interrupt clears PD bit and exits Power Down mode, after the ISR RETI instruction program resumes execution beginning at the instruction following the one that invoked Power Down mode. If needed in a specific application, a user could consider placing two or three NOP instructions after the instruction that invokes Power Down mode to eliminate any problems. A hardware reset restarts the device similar to a poweron reset. Gate ON external clock. Program execution resumes at the instruction following the one during which the clock was gated off.
344 PGM T10.3
Power Down Mode
Software (Set PD bit in PCON)
Typically 15 microamps. CLK is stopped. OnMinimum VDD for Power chip SRAM and SFR Down mode is 2.7V. data is maintained. ALE and PSEN# signals at a LOW level during Power Down. External Interrupts are only active for level sensitive interrupts, if enabled.
Standby (Stop Clock) Mode
Typically 15 microamps. External hardware gates OFF the external Minimum VDD for clock input to the MCU. Standby mode is 2.7V. This gating should be synchronized with an input clock transition (low-to-high or high-tolow).
CLK is frozen. On-chip SRAM and SFR data is maintained. ALE and PSEN# are maintained at the levels prior to the clock being frozen.
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Preliminary Specifications CLOCK INPUT OPTIONS Shown in Figure 21 are the input and output of an internal inverting amplifier (XTAL1, XTAL2), which can be configured for use as an on-chip oscillator. When driving the device from an external clock source, XTAL2 should be left disconnected and XTAL1 should be driven. At start-up, the external oscillator may encounter a higher capacitive load at XTAL1 due to interaction between the amplifier and its feedback capacitance. However, the capacitance will not exceed 15pF once the external signal meets the VIL and VIH specifications. Recommended Capacitor Values for Crystal Oscillator Crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one application to another. C1 and C2 should be adjusted appropriately for each design. The table below, shows the typical values for C1 and C2 at a given frequency. If, following the satisfactory selection of all external components, the circuit is still over driven, a series resistor, Rs, may be added. RECOMMENDED VALUES FOR CRYSTAL OSCILLATOR Frequency < 8MHz 8-12MHz >12MHz C1 and C2 90-110pF 18-22pF 18-22pF Rs (Optional) 100W 200W 200W
1 2 3 4 5 6 7 8
More specific information on On-Chip oscillator design can be found in FlashFlex51 Oscillator Circuit Design Considerations Application Note.
RS C2 C1
XTAL2 NC EXTERNAL OSCILLATOR SIGNAL XTAL2 XTAL1 Vss
9 10 11
XTAL1 Vss
Using the On-Chip Oscillator
External Clock Drive
344 ILL F12.1
12 13
FIGURE 21: OSCILLATOR CHARACTERISTICS
14 15 16
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Preliminary Specifications ELECTRICAL SPECIFICATION Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Ambient Temperature Under Bias ................................................................................................... -55C to +125C Storage Temperature ..................................................................................................................... -65C to + 150C Voltage on EA# Pin to VSS ...................................................................................................................................................... -0.5V to +14.0V Transient Voltage (<20ns) on Any Other Pin to VSS ..................................................................................................... -1.0V to +6.5V Maximum IOL per I/O Pins P1.5, P1.6, P1.7 ...................................................................................................... 20mA Maximum IOL per I/O for All Other Pins............................................................................................................. 15mA Package Power Dissipation Capability (TA = 25C) ........................................................................................... 1.5W Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300C Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240C Output Short Circuit Current(1) ................................................................................................................................................................... 50mA
Note (1) Outputs shorted for no more than one second. No more than one output shorted at a time. (Based on package heat transfer limitations, not device power consumption.) NOTICE: This specification contains preliminary information on new products in production. The specifications are subject to change without notice.
Operation Range TABLE 11: OPERATING RANGE Symbol Description TA Ambient Temperature Under Bias Standard Industrial VDD Supply Voltage fOSC Oscillator Frequency For In-Application Programming TABLE 12: RELIABILITY CHARACTERISTICS Symbol Parameter NEND TDR(1) VZAP_HBM(1) VZAP_MM(1) ILTH(1)
Note:
(1)This
Min. 0 -40 2.7 0 0.25
Max +70 +85 5.5 33 33
Unit C C V MHz MHz
344 PGM T11.0
Minimum Specification 10,000 100 2000 200 100+IDD
Units Cycles Years Volts Volts mA
Test Method MIL-STD-883, Method 1033 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
344 PGM T12.1
Endurance Data Retention ESD Susceptibility Human Body Model ESD Susceptibility Machine Model Latch Up
parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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Preliminary Specifications TABLE 13A: DC ELECTRICAL CHARACTERISTICS TAMB = OC TO + 70C OR -40C TO +85C, 33MHZ DEVICES; 5V 10%; VSS = 0V Symbol VIL VIH VIH1 VOL VOL Parameter Input Low Voltage Input High Voltage (ports 0,1,2,3) Input High Voltage (XTAL1, RST) Output Low Voltage (Ports 1.5, 1.6, 1.7) Output Low Voltage (Ports 1, 2, 3) 5 Test Conditions Min 4.5 < VDD < 5.5 4.5 < VDD < 5.5 4.5 < VDD < 5.5 VDD = 4.5V IOL = 16mA VDD = 4.5V IOL = 100A 1 IOL = 1.6mA 1 IOL = 3.5mA 1 VDD = 4.5V IOL = 200A 1 IOL = 3.2mA 1 VDD = 4.5V IOH = -10A IOH = -30A IOH = -60A VDD = 4.5V IOH = -200A IOH = -3.2mA VIN = 0.4V VIN = 2V 0.45 < VIN < VDD-0.3 40 @ 1 MHz, 25C -0.5 0.2VDD + 0.9 0.7VDD Limits Max 0.2VDD - 0.1 VDD + 0.5 VDD + 0.5 1.0 0.3 0.45 1.0 0.3 0.45 VDD - 0.3 VDD - 0.7 VDD - 1.5 VDD - 0.3 VDD - 0.7 -1 V V V V V V V V V V V V V V A A A kW pF Units
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VOL1
Output Low Voltage (Port 0, ALE, PSEN#) 4,5 Output High Voltage (Ports 1, 2, 3, ALE, PSEN#) 2
VOH
VOH1
Output High Voltage (Port 0 in External Bus Mode) 2 Logical 0 Input Current (Ports 1, 2, 3) Logical 1-to-0 Transition Current (Ports 1, 2, 3) 3 Input Leakage Current (Port 0) RST Pulldown Resistor Pin Capacitance6 Power Supply Current 7 In-Application Mode @ 12 MHz @ 33 MHz Active Mode @ 12 MHz @ 33 MHz Idle Mode @ 12 MHz @ 33 MHz Standby (Stop Clock) Mode Power Down Mode
IIL ITL ILI RRST CIO IDD
-75 -650 10 225 15
70 88 25 45 12 24 100 125 40 50
mA mA mA mA mA mA A A A A
344 PGM T13A.5
Tamb =0C to + 70C Tamb =-40C to +85C
Minimum VDD = 2.7V
Tamb =0C to + 70C Tamb =-40C to +85C
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications TABLE 13B: DC ELECTRICAL CHARACTERISTICS TAMB = OC TO + 70C OR -40C TO +85C, 12 MHZ DEVICES; 3V 10%; VSS = 0V Symbol VIL VIH VIH1 VOL VOL Parameter Input Low Voltage Input High Voltage (ports 0,1,2,3) Input High Voltage (XTAL1, RST) Output Low Voltage (Ports 1.5, 1.6, 1.7) Output Low Voltage (Ports 1, 2, 3) 5 Test Conditions Min 2.7 < VDD < 3.3 2.7 < VDD < 3.3 2.7 < VDD < 3.3 VDD = 2.7V IOL = 16mA VDD = 2.7V IOL = 100A 1 IOL = 1.6mA 1 IOL = 3.5mA 1 VDD = 2.7V IOL = 200A 1 IOL = 3.2mA 1 VDD = 2.7V IOH = -10A IOH = -30A IOH = -60A VDD = 2.7V IOH = -200A IOH = -3.2mA VIN = 0.4V VIN = 2V 0.45 < VIN < VDD-0.3 40 @ 1 MHz, 25C -0.5 0.2VDD + 0.9 0.7VDD Limits Max 0.7 VDD + 0.5 VDD + 0.5 1.0 0.3 0.45 1.0 0.3 0.45 VDD - 0.3 VDD - 0.7 VDD - 1.5 VDD - 0.3 VDD - 0.7 -1 V V V V V V V V V V V V V V A A A kW pF mA mA mA A A A A
344 PGM T13B.3
Units
VOL1
Output Low Voltage (Port 0, ALE, PSEN#) 4,5 Output High Voltage (Ports 1, 2, 3, ALE, PSEN#) 2
VOH
VOH1
Output High Voltage (Port 0 in External Bus Mode) 2 Logical 0 Input Current (Ports 1, 2, 3) Logical 1-to-0 Transition Current (Ports 1, 2, 3) 3 Input Leakage Current (Port 0) RST Pulldown Resistor Pin Capacitance6 Power Supply Current 7 In-Application Mode Active Mode Idle Mode Standby (Stop Clock) Mode Power Down Mode
IIL ITL ILI RRST CIO IDD
-75 -650 10 225 15 70 22 6.5 70 88 40 50
Tamb =0C to + 70C Tamb =-40C to +85C
Minimum VDD = 2.7V
Tamb =0C to + 70C Tamb =-40C to +85C
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications
NOTES: 1. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 & 3. The noise due to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1 -to- 0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 2. Capacitive loading on Ports 0 & 2 may cause the VOH on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when the address bits are stabilizing. 3. Pins of Ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when Vin is approximately 2V. 4. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs= 80pF. 5. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA 26mA Maximum IOL per 8-bit port: Maximum IOL total for all outputs: 71mA If IOL exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 6. Pin capacitance is characterized but not tested. EA# is 25pF (max). 7. See Figures 22, 23, 24 and 25 for test conditions. Minimum VDD for Power Down is 2.7V.
VDD IDD
VDD
1 2 3 4 5
VDD VDD RST 8XC5X CLOCK SIGNAL (NC) XTAL2 XTAL1 VSS P0 EA#
VDD
VDD P0 RST 8XC5X CLOCK SIGNAL (NC) XTAL2 XTAL1 VSS EA#
IDD
VDD
6 7 8
344 ILL F26.0
344 ILL F24.0
All other pins disconnected
All other pins disconnected
9 10 11 12 13 14
FIGURE 22: IDD TEST CONDITION, ACTIVE MODE
FIGURE 23: IDD TEST CONDITION, IDLE MODE
VDD = 3 or 5V VDD P0 RST 8XC5X (NC) XTAL2 XTAL1 VSS EA#
VDD IDD VDD
VDD = 5V VDD P0 RST 8XC5X (NC) XTAL2 XTAL1 VSS EA#
VDD IDD VDD
344 ILL F25.2
344 ILL F33.3
All other pins disconnected
All other pins disconnected
15
FIGURE 25: IDD TEST CONDITION, STANDBY (STOP CLOCK) MODE
FIGURE 24: IDD TEST CONDITION, POWER DOWN MODE
16
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications AC ELECTRICAL CHARACTERISTICS AC Characteristics: (Over Operating Conditions; Load Capacitance for Port 0, ALE, and PSEN# = 100pF; Load Capacitance for All Other Outputs = 80pF) TABLE 14: AC ELECTRICAL CHARACTERISTICS TAMB = 0C TO +70C OR -40C TO +85C, VDD = 3V10% @ 12MHZ, 5V10% @ 33MHZ, VSS = 0 Symbol Parameter 12MHz Min Max
1/TCLCL TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TWHQX TQVWH TRLAZ TWHLH Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instr In ALE Low to PSEN# Low PSEN# Pulse Width PSEN# Low to Valid Instr In Input Instr Hold After PSEN# Input Instr Float After PSEN# Address to Valid Instr In PSEN# Low to Address Float RD# Pulse Width Write Pulse Width (WE#) RD# Low to Valid Data In Data Hold After RD# Data Float After RD# ALE Low to Valid Data In Address to Valid Data In ALE Low to RD# or WR# Low Address to RD# or WR# Low Data Valid to WR# Transition Data Hold After WR# Data Valid to WR# High RD# Low to Address Float RD# to WR# High to ALE High 200 203 33 0 33 3 433 140 43 0 123 5 0 55 TCLCL - 40 (5V) TCLCL - 25 (3V) 53 205 145 35 0 59 5 312 10 400 400 252 61 0 107 35 517 150 585 300 40 46 180 140 3TCLCL - 50 4TCLCL - 130 (5V) 4TCLCL - 75 (3V) TCLCL - 50 (5V) TCLCL - 30 (3V) TCLCL - 50 (5V) TCLCL - 27 (3V) 7TCLCL - 150 (5V) 7TCLCL - 70 (3V) 0 0 2TCLCL - 60 (5V) 2TCLCL - 25 (3V) 8TCLCL - 150 (5V) 8TCLCL - 90 (3V) 9TCLCL - 165 (5V) 9TCLCL - 90 (3V) 3TCLCL + 50 82 82 71 10 6TCLCL - 100 6TCLCL - 100 5TCLCL - 165 (5V) 5TCLCL - 90 (3V) TCLCL - 25 (5V) TCLCL - 25 (3V) 5TCLCL - 105 (5V) 5TCLCL - 80 (3V) 10 5 46 127 43 53 5 234 56 TCLCL - 30 (5V) TCLCL - 25 (3V) 3TCLCL - 45 3TCLCL - 105 (5V) 3TCLCL - 55 (3V)
Oscillator 33MHz Min Max
20 5
Units Variable Min.
0
Max.
33 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
344 PGM T14.2
2TCLCL - 40 TCLCL - 40 (5V) TCLCL - 25 (3V) TCLCL - 30 (5V) TCLCL - 25 (3V) 4TCLCL - 100 (5V) 4TCLCL - 65 (3V)
0 TCLCL + 40 (5V) TCLCL + 25 (3V)
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications AC CHARACTERISTICS Explanation of Symbols Each timing symbol has 5 characters. The first character is always a `T' (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: Address C: Clock D Input data H: Logic level HIGH I: Instruction (program memory contents). L: Logic level LOW or ALE P: PSEN# Q: Output data R: RD# signal T: Time V: Valid W: WR# signal X: No longer a valid logic level Z: High Impedance (Float) For example: TAVLL=Time from Address Valid to ALE Low TLLPL=Time from ALE Low to PSEN# Low
1 2 3 4 5 6
VIHT
VHT VLT
344 ILL F28a.2
VLOAD +0.1V VLOAD VLOAD -0.1V Timing Reference Points
VOH -0.1V VOL +0.1V
344 ILL F28b.1
7 8 9
VILT
AC Inputs during testing are driven at VIHT (VDD -0.5V) for Logic "1" and VILT (0.45V) for a Logic "0". Measurement reference points for inputs and outputs are at VHT (0.2VDD + 0.9) and VLT (0.2VDD - 0.1)
Note: VHT- VHIGH Test VLT- VLOW Test VIHT-VINPUT HIGH Test VILT- VINPUT LOW Test
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH = 20mA.
AC TESTING INPUT/OUTPUT FIGURE 26: AC TESTING INPUT/OUTPUT, FLOAT WAVEFORM
FLOAT WAVEFORM
10 11
TLHLL
ALE
TAVLL TLLPL TPLAZ TLLAX TLLIV TPLIV TPXIZ TPXIX INSTR IN A7 - A0 TPLPH
12 13 14
A15 - A8
344 ILL F13.3
PSEN#
PORT 0
A7 - A0 TAVIV
PORT 2
A15 - A8
15 16
FIGURE 27: EXTERNAL PROGRAM MEMORY READ CYCLE
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications
TLHLL
ALE
TWHLH
PSEN#
TLLDV TRLRH TLLWL
RD#
TAVLL
TLLAX TRLAZ TRLDV
TRHDZ TRHDX
PORT 0
A7-A0 FROM RI or DPL TAVWL TAVDV
DATA IN
A7-A0 FROM PCL
INSTR IN
PORT 2
P2[7:0] or A15-A8 FROM DPH
A15-A8 FROM PCH
344 ILL F14.3
FIGURE 28: EXTERNAL DATA MEMORY READ CYCLE
TLHLL
ALE
TWHLH
PSEN#
TLLWL TWLWH
WR#
TAVLL
TLLAX TQVWX TQVWH
TWHQX
PORT 0
A7-A0 FROM RI or DPL TAVWL
DATA OUT
A7-A0 FROM PCL
INSTR IN
PORT 2
P2[7:0] or A15-A8 FROM DPH
A15-A8 FROM PCH
344 ILL F15.3
FIGURE 29: EXTERNAL DATA MEMORY WRITE CYCLE TABLE 15: EXTERNAL CLOCK DRIVE Symbol Parameter 12MHz Min Max 1/TCLCL TCHCX TCLCX TCLCH TCHCL Oscillator Frequency High Time Low Time Rise Time Fall Time
Oscillator 33MHz Min Max Variable Min. 0 0.35TCLCL 0.35TCLCL Max. 33 0.65TCLCL 0.65TCLCL
Units
20 20
5 5
MHz ns ns ns ns
344 PGM T15.2
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications
VDD = -0.5
0.7 VDD 0.2 VDD -0.1 TCLCX TCHCL TCLCL TCHCX TCLCH
344 ILL F30.0
1 2 3
0.45 V
FIGURE 30: EXTERNAL CLOCK DRIVE WAVEFORM
4
TABLE 16: SERIAL PORT TIMING Symbol Parameter 12MHz Min Max 0 700 50 10 0 700 0 167
5
Oscillator 33MHz Min Max 0.36 167 Variable Min. 12TCLCL 10TCLCL - 133 2TCLCL - 117 2TCLCL - 50 0 10TCLCL - 133 Max. ms Units
6 7
ns ns ns ns ns
TXLXL TQVXH TXHQX TXHDX TXHDV
Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid
8 9 10
344 PGM T16.1
11
INSTRUCTION ALE TXLXL
0 1 2 3 4 5 6 7 8
12
TXHQX
CLOCK
TQVXH
OUTPUT DATA WRITE TO SBUF INPUT DATA CLEAR RI
0
1
TXHDV VALID VALID
2
TXHDX VALID
3
4
5
6
7
SET TI
13 14 15 16
VALID
VALID
VALID
VALID
VALID
SET R I
344 ILL F29.0
FIGURE 31: SHIFT REGISTER MODE TIMING WAVEFORMS
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications PRODUCT ORDERING INFORMATION Device SST89C5x Product Identification Descriptor Speed Suffix 1 Suffix 2 - 33 - XX - XX Package Modifier I = 40 pins J = 44 pins Package Type P = PDIP N = PLCC TQ = TQFP Operation Temperature C = Commercial = 0 to 70C I = Industrial = -40 to 85C Release ID Blank = Initial release A = First enhancement Operating Frequency 33 = 0-33MHz Feature Set and Flash Memory Size 54 = C52 feature set + 16(20)* KByte 58 = C52 feature set + 32(36)* KByte * = 4K additional flash can be enabled via VIS bit in SFCF Voltage Range C = 2.7-5.5V Device Family 89 = C51 Core Part Number Valid Combinations SST89C54 Valid combinations Part Number SST89C54-33-C-PI SST89C54-33-C-NJ SST89C54-33-C-TQJ SST89C54-33-I-PI SST89C54-33-I-NJ SST89C54-33-I-TQJ SST89C58 Valid combinations Part Number SST89C58-33-C-PI SST89C58-33-C-NJ SST89C58-33-C-TQJ SST89C58-33-I-PI SST89C58-33-I-NJ SST89C58-33-I-TQJ
Package PDIP PLCC TQFP PDIP PLCC TQFP Package PDIP PLCC TQFP PDIP PLCC TQFP
Pins 40 44 44 40 44 44 Pins 40 44 44 40 44 44
VDD 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 VDD 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5 2.7-5.5
Speed 0-33MHz 0-33MHz 0-33MHz 0-33MHz 0-33MHz 0-33MHz Speed 0-33MHz 0-33MHz 0-33MHz 0-33MHz 0-33MHz 0-33MHz
Temperature Commercial Commercial Commercial Industrial Industrial Industrial Temperature Commercial Commercial Commercial Industrial Industrial Industrial
Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability and to determine availability of new combinations.
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications Part Number Cross-Reference Guide
Intel i87C54 i87C58 i87L54 i87L58 i87C51FB i87C51FC Atmel AT89C52 AT89LV52 AT89S53 AT89LS53 AT89C55 AT89LV55 Temic 80C51 80C52 83C154 83C154D 87C51 87C52 Philips P80C54 P80C58 P87C54 P87C58 P87C524 P87C528 P83C524 P83C528 P89CE558 Winbond W78C54 W78C58 W78E54 W78E58 ISSI IS80C52 IS89C51 IS89C52 Dallas DS83C520 DS87C520 256B RAM Siemens C501-1R C501-1E C513A-H C503-1R C504-2R SST SST89C54 SST89C58 SST89C54 SST89C58 SST89C54* SST89C58* SST SST89C54 SST89C54 SST89C54* SST89C54* SST89C58* SST89C58* SST SST89C54* SST89C54 SST89C54 SST89C58 SST89C54* SST89C54 SST SST89C54 SST89C58 SST89C54 SST89C58 SST89C54* SST89C58* SST89C54* SST89C58* SST89C58* SST SST89C54 SST89C58 SST89C54 SST89C58 SST SST89C54 SST89C54 SST89C54 SST SST89C54* SST89C54* package P N TQ P N TQ N TQ N TQ P N TQ P N TQ package P N TQ P N TQ P N TQ P N TQ P N TQ P N TQ package P N TQ P N TQ P N TQ P N TQ P N TQ P N TQ package P N TQ P N TQ P N TQ P N TQ P N TQ P N TQ PN P N TQ
16K EPROM & 256B RAM 32K EPROM & 256B RAM 16K ROM (OTP) & 256B RAM 32K ROM (OTP) & 256B RAM 16K EPROM & 256B RAM 32K EPROM & 256B RAM
4K Flash, 16K Flash & 256B RAM 4K Flash, 32K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 32K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 32K Flash & 256B RAM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
8K Flash & 256B RAM 8K Flash & 256B RAM 12K Flash & 256B RAM 12K Flash & 256B RAM 20K Flash & 256B RAM 20K Flash & 256B RAM
4K Flash, 16K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 32K Flash & 256B RAM 4K Flash, 32K Flash & 256B RAM
4K ROM & 256B RAM 8K ROM & 256B RAM 16K ROM & 256B RAM 32K ROM & 256B RAM 4K EPROM & 256B RAM 8K EPROM & 256B RAM
4K Flash, 16K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 32K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM
16K ROM & 256B RAM 32K ROM & 256B RAM 16K EPROM & 256B RAM 32K EPROM & 256B RAM 16K EPROM & 512B RAM 32K EPROM & 512B RAM 16K ROM & 512B RAM 32K MROM & 512B RAM 32K Flash & 1K RAM
4K Flash, 16K Flash & 256B RAM 4K Flash, 32K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 32K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 32K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 32K Flash & 256B RAM 4K Flash, 32K Flash & 256B RAM
16K MROM & 256B RAM 32K MROM & 256B RAM 16K EEPROM & 256B RAM 32K EEPROM & 256B RAM
4K Flash, 16K Flash & 256B RAM 4K Flash, 32K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 32K Flash & 256B RAM
package P N TQ P N TQ P N TQ P N TQ package P N TQ PN PN package P N TQ P N TQ
8K ROM & 256B RAM 4K Flash & 128B RAM 8K Flash & 256B RAM
4K Flash, 16K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM
16K MROM & 256B RAM 16K EPROM ( OTP ) &
4K Flash, 16K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM
8K ROM & 256B RAM 8K ROM (OTP) & 256B RAM 12K EPROM & 512B RAM 8K ROM & 256B RAM 16K ROM & 512B RAM
SST SST89C54 SST89C54 SST89C54* SST89C54* SST89C54*
4K Flash, 16K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM 4K Flash, 16K Flash & 256B RAM
package PN PN N N TQ
P: PDIP N: PLCC TQ: TQFP
NOTE: NOTE: The SST89C58 can be substituted for any SST89C54 listing above. The SST89C59 can be substituted for any SST89C54 or SST89C58 listing above. * Indicates SST similar function and not direct replacement/socket compatible.
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications PACKAGING DIAGRAMS
40
C L
1 Pin #1 Identifier
2.020 2.070
.600 .625 .530 .557
.065 .075
12 4 places
Base Plane Seating Plane
.015 Min.
.220 Max.
.063 .090
.045 .055
.015 .022
.100 BSC
.100 .200
.008 .012 .600 BSC
0 15
Note:
1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent. = JEDEC min is .115; SST min is less stringent 40.pdipPI-ILL.6 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
40-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PI
TOP VIEW
.685 .695 .646 .656
1 44
SIDE VIEW
BOTTOM VIEW
Optional Pin #1 Identifier .042 .048
.020 R. MAX. .042 x45 .056
.147 .158 .025 R. .045
.042 .048 .685 .695 .646 .656 .026 .032
.013 .021 .500 REF. .590 .630
.050 BSC. .020 Min. .026 .032
44.PLCC.NJ-ILL.6
.050 BSC. .165 .180
.100 .112
Note:
1. Complies with JEDEC publication 95 MS-018 AC dimensions (except as noted), although some dimensions may be more stringent. = JEDEC min is .650; SST min is less stringent 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils.
44-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NJ
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications
1 2
33 34 23 22
.020
3 4
.80 BSC 10.0 12.0 BSC BSC 1.20 1.05 max. .95 .75 .45 1.00 ref .09 .20 0- 7
5 6 7
.30 .45
44 1
Pin 1 Identifier(s) (either or both)
12 11
.30 .45 10.0 BSC 12.0 BSC 0.20
.15 .05
.80 BSC
44.tqfp-TQJ-ILL.3
8 9 10 11 12 13 14 15 16
Note:
1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in mm (min/max). 3. Coplanarity: 0.1 (0.05) mm.
44-LEAD THIN QUAD FLAT PACK (TQFP) SST PACKAGE CODE: TQJ
(c) 2000 Silicon Storage Technology, Inc.
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FlashFlex51 MCU SST89C54 / SST89C58
Preliminary Specifications
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com * Literature FaxBack 888-221-1178, International 732-544-2873
(c) 2000 Silicon Storage Technology, Inc.
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